A CPU Simulator based on FPGA soft processor
Cesar A. Vera Bernal
Francisco J. Guerra Manchego
Paola T. Llerena Valdivia
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A CPU Simulator based on FPGA soft processor | ||
| Published in: | Engineering for a Smarter Planet: Innovation, ITC, and Computational Tools for Sustainable Development: Proceedings of the 9th Latin American and Caribbean Conference for Engineering and Technology | |
| Date of Conference: | August 3-5, 2011 | |
| Location of Conference: | Medellin, Colombia | |
| Authors: | Raul R. Peralta Meza Cesar A. Vera Bernal Francisco J. Guerra Manchego Paola T. Llerena Valdivia | |
| Refereed Paper: | #248 | |
Abstract | ||
| The CPU simulators has become an important aspect of teaching computer architecture since they show to the students the execution of a program inside of a particular processor. However, the majority of them are not user friendly and do not show the logic circuits inside the processor working together in order to execute an instruction. The purpose of this paper is to present the design and implementation of a CPU Simulator that meets those requirements. The simulator is based in a FPGA soft processor, a multi-cycle processor in VHDL, that has been tested on the top of SPARTAN-3E development board. The FPGA soft processor was reprogrammed in C++ because a graphical user interface (GUI) and a compiler were added to the simulator. In this fashion the simulator users could understand and learn the interaccions between the Instruction Set Architecture (ISA) of the processor with its lower levels of hardware (datapath and control unit). | ||